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May 1997
Features
S IG N DES EW t RN ter a D FO 5 Cen sc DE N 17 ort t MME ee HI1 l Supp il.com/ S ni c a ECO rs R te h w .in N OT Te c ou r L or w w ct RSI onta or c 8-INTE 1-88
(R)
HI-5700
8-Bit, 20 MSPS Flash A/D Converter
Description
The HI-5700 is a monolithic, 8-bit, CMOS Flash Analog-toDigital Converter. It is designed for high speed applications where wide bandwidth and low power consumption are essential. Its 20 MSPS speed is made possible by a parallel architecture which also eliminates the need for an external sample and hold circuit. The HI-5700 delivers 0.5 LSB differential nonlinearity while consuming only 725mW (typical) at 20 MSPS. Microprocessor compatible data output latches are provided which present valid data to the output bus 1.5 clock cycles after the convert command is received. An overflow bit is provided to allow the series connection of two converters to achieve 9-bit resolution.
* 20 MSPS with No Missing Codes * 18MHz Full Power Input Bandwidth * No Missing Codes Over Temperature * Sample and Hold Not Required * Single +5V Supply Voltage * CMOS/TTL * Overflow Bit * Improved Replacement for MP7684 * Evaluation Board Available * /883 Version Available
Ordering Information
PART NUMBER HI3-5700J-5 HI9P5700J-5 HI3-5700A-9 HI9P5700A-9 TEMPERATURE RANGE 0oC to +70oC 0 C to +70 C
o o
Applications
* Video Digitizing * Radar Systems * Medical Imaging * Communication Systems * High Speed Data Acquisition Systems
PACKAGE 28 Lead Plastic DIP 28 Lead Plastic SOIC (W) 28 Lead Plastic DIP 28 Lead Plastic SOIC (W)
-40 C to +85 C
-40oC to +85oC
o
o
Pinout
HI-5700 (PDIP, SOIC) TOP VIEW
CLK 1 (MSB) D7 2 D6 3 D5 4 D4 5
1
28 VIN 27 VREF 26 AVDD 25 AGND 24 AGND 23 AVDD 22
1
/4R 6 7
VDD
3
/2R
GND 8 /4R 9
21 AVDD 20 AGND 19 AGND 18 AVDD 17 VREF + 16 CE1 15 CE2
D3 10 D2 11 (LSB) D1 12 D0 13 OVF 14
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
File Number
3174.4
HI-5700 Functional Block Diagram
y1 y2
y1
y1
y2
VIN 28 VREF + 17 R/2 R D Q CL COMP 256 14 OVERFLOW (OVF)
D Q CL
2
D7 (MSB)
R
3
/4R
9 R COMP 193 R
D Q CL
3
D6
1
/2R 22 R COMP 129
COMPARATOR LATCHES AND ENCODER LOGIC
D Q CL
4
D5
R
1
D Q CL
5
D4
/4R
6 R COMP 65 D Q CL 10 D3
R
D Q CL COMP 2
11 D2
R
D Q CL
12 D1
VREF - 27
R/2 COMP 1
D Q CL
13
D0 (LSB)
16 CE1 15 CE2
y1
CLK 1
VDD 7
GND
AVDD 23
AGND
21 25
26 19
18 20
y2
8
24
4-1492
Specifications HI-5700
Absolute Maximum Ratings
Supply Voltage, V DD to GND . . . . . . . . . (GND - 0.5) < VDD < +7.0V Analog and Reference Input Pins . . . .(VSS - 0.5) < VINA < (VDD +0.5V) Digital I/O Pins . . . . . . . . . . . . . . . (GND - 0.5) < VI/O < (VDD +0.5V) Storage Temperature Range . . . . . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Thermal Information
Thermal Resistance JA HI3-5700J-5, HI3-5700A-9 . . . . . . . . . . . . . . . . . . . . . 55oC/W HI9P5700J-5, HI9P5700A-9 . . . . . . . . . . . . . . . . . . . . 75oC/W Maximum Power Dissipation +70oC . . . . . . . . . . . . . . . . . . . . 1.05W Operating Temperature Range HI3-5700J-5, HI9P5700J-5 . . . . . . . . . . . . . . . . . . . 0oC to +70oC HI3-5700A-9, HI9P5700A-9 . . . . . . . . . . . . . . . -40oC to +85oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC
CAUTION: Stresses above those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied.
Electrical Specifications
AVDD = VDD = +5.0V; VREF+ = +4.0V; VREF- = GND = AGND = 0V; FS = Specified Clock Frequency at 50% Duty Cycle; C L = 30pF; Unless Otherwise Specified (NOTE 2) 0o C TO +70oC -40oC TO +85oC MAX MIN MAX UNITS
+25oC PARAMETER SYSTEM PERFORMANCE Resolution Integral Linearity Error (INL) (Best Fit Method) Differential Linearity Error (DNL) (Guaranteed No Missing Codes) Offset Error (VOS) Full Scale Error (FSE) DYNAMIC CHARACTERISTICS Maximum Conversion Rate Minimum Conversion Rate Full Power Input Bandwidth Signal to Noise Ratio (SNR) RM S Signal = -------------------------------RMS Noise No Missing Codes No Missing Codes (Note 2) FS = 20MHz FS = 15MHz, fIN FS = 15MHz, fIN FS = 15MHz, fIN FS = 20MHz, fIN FS = 20MHz, fIN FS = 20MHz, fIN FS = 15MHz, fIN FS = 15MHz, fIN FS = 15MHz, fIN FS = 20MHz, fIN FS = 20MHz, fIN FS = 20MHz, fIN FS = 15MHz, fIN FS = 15MHz, fIN FS = 15MHz, fIN FS = 20MHz, fIN FS = 20MHz, fIN FS = 20MHz, fIN = 100kHz = 3.58MHz = 4.43MHz = 100kHz = 3.58MHz = 4.43MHz = 100kHz = 3.58MHz = 4.43MHz = 100kHz = 3.58MHz = 4.43MHz = 100kHz = 3.58MHz = 4.43MHz = 100kHz = 3.58MHz = 4.43MHz 20 25 18 46.5 44.0 43.4 45.9 42.0 41.6 43.4 34.3 32.3 42.3 35.2 32.8 -46.9 -34.8 -32.8 -46.6 -36.6 -33.5 3.5 0.9 0.125 FS = 15MHz, fIN = DC FS = 20MHz, fIN = DC FS = 15MHz, fIN = DC FS = 20MHz, fIN = DC FS = 15MHz, fIN = DC FS = 20MHz, fIN = DC FS = 15MHz, fIN = DC FS = 20MHz, fIN = DC 8 0.9 1.0 0.4 0.5 5.0 5.0 0.5 0.6 2.0 2.25 0.9 0.9 8.0 8.0 4.5 4.5 TEST CONDITION MIN TYP
8 -
2.25 3.25 1.0 1.0 9.5 9.5 8.0 8.0
Bits LSB LSB LSB LSB LSB LSB LSB LSB
20 -
0.125 -
MSPS MSPS MHz dB dB dB dB dB dB dB dB dB dB dB dB dBc dBc dBc dBc dBc dBc % Degree
Signal to Noise and Distortion Ratio (SINAD) RM S Signal = ------------------------------------------------------------RMS Noise + Distortion
Total Harmonic Distortion (THD)
Differential Gain Differential Phase Error
FS = 14MHz, fIN = 3.58MHz FS = 14MHz, fIN = 3.58MHz
4-1493
Specifications HI-5700
Electrical Specifications
AVDD = VDD = +5.0V; VREF+ = +4.0V; VREF- = GND = AGND = 0V; FS = Specified Clock Frequency at 50% Duty Cycle; C L = 30pF; Unless Otherwise Specified (Continued) (NOTE 2) 0o C TO +70oC -40oC TO +85oC MAX MIN MAX UNITS
+25oC PARAMETER ANALOG INPUTS Analog Input Resistance, RIN Analog Input Capacitance, CIN Analog Input Bias Current, IB REFERENCE INPUTS Total Reference Resistance, RL Reference Resistance Tempco, TC DIGITAL INPUTS Input Logic High Voltage, VIH Input Logic Low Voltage, VIL Input Logic High Current, IIH Input Logic Low Current, IIL Input Capacitance, CIN DIGITAL OUTPUTS Output Logic Sink Current, IOL Output Logic Source Current, IOH Output Leakage, IOZ Output Capacitance, COUT TIMING CHARACTERISTICS Aperture Delay, tAP Aperture Jitter, tAJ Data Output Enable Time, tEN Data Output Disable Time, tDIS Data Output Delay, tOD Data Output Hold, tH POWER SUPPLY REJECTION Offset Error PSRR, VOS Gain Error PSRR, FSE POWER SUPPLY CURRENT Supply Current, IDD NOTES: 9. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. 10. Parameter guaranteed by design or characterization and not production tested. FS = 20MHz 145 180 VDD = 5V 10% VDD = 5V 10% 0.1 0.1 2.75 2.75 10 6 30 18 15 20 20 25 20 25 VO = 0.4V VO = 4.5V CE2 = 0V, VO = 0V, 5V CE2 = 0V 3.2 2.0 7 0.8 1.0 1.0 250 330 +0.31 VIN = 4V VIN = 0V VIN = 0V, 4V 4 10 60 0.01 TEST CONDITION MIN TYP
1.0
-
1.0
M pF A
235 -
-
/C
VIN = 5V VIN = 0V
2.0 -
0.8 1.0 1.0 -
V V A A pF
-3.2
-
5.0
1.0 -
3.2
-3.2
-
1.0 -
mA mA A pF
5
30 25 30 -
ns ps ns ns ns ns
-
5.0 5.0
LSB LSB
-
190
mA
4-1494
HI-5700 Timing Waveforms
COMPARATOR DATA IS LATCHED CLOCK INPUT SAMPLE N-2 SAMPLE N-1 SAMPLE N SAMPLE N+1 ENCODER DATA IS LATCHED INTO THE OUTPUT REGISTERS SAMPLE N+2
AUTO BALANCE tAB
AUTO BALANCE
AUTO BALANCE
AUTO BALANCE
ANALOG INPUT
tAP tH tAJ tOD
DATA OUTPUT
DATA N-4
DATA N-3
DATA N-2
DATA N-1
DATA N
FIGURE 1. INPUT-TO-OUTPUT TIMING
CE1
CE2 tEN tDIS tEN
tDIS D0 - D7 DATA HIGH
IMPEDANCE
DATA
HIGH IMPEDANCE
DATA
OVF
DATA
HIGH IMPEDANCE
DATA
FIGURE 2. OUTPUT ENABLE TIMING
4-1495
HI-5700 Typical Performance Curves
8 VDD = 5V, VREF+ = 4V TA = 25o C 7 EFFECTIVE BITS EFFECTIVE BITS 7 FS = 20MHz, fIN = 100kHz 6 FS = 20MHz, fIN = 3.85MHz 5 FS = 15MHz, fIN = 3.85MHz 8 VDD = 5V, VREF + = 4V
FS = 15MHz, fIN = 100kHz
6 FS = 20MHz 5
FS = 15MHz
4 0 0.5 1 1.5 2 2.5 3 3.5 INPUT FREQUENCY - fIN (MHz) 4 4.5 5
4 -60 -40 -20 0 +20 +40 +60 +80 +100 +120 +140 TEMPERATURE (oC)
FIGURE 3. EFFECTIVE NUMBER OF BITS vs fIN
FIGURE 4. EFFECTIVE NUMBER OF BITS vs TEMPERATURE
50 48 46 44 42 40
VDD = 5V, VREF+ = 4V
-30 A. -32 -34 B. -36 -38
VDD = 5V, VREF+ = 4V
B. D.
38 A. 36 B. C. 34 D. 32 30 28 26 -60
FS = 15MHz, FS = 15MHz, FS = 20MHz, FS = 20MHz,
fIN = 100kHz fIN = 4.43MHz fIN = 100kHz fIN = 4.43MHz
dBc
dB
C.
-40 -42 -44
A. F S = 15MHz, fIN = B. F S = 15MHz, fIN = C. F S = 20MHz, fIN = D. F S = 20MHz, fIN =
100kHz 4.43MHz 100kHz 4.43MHz
C.
A.
D.
-46 -48 -50 -60 -40 -20 0 +20 +40 +60 +80 +100 +120 +140
-40
-20
0
+20
+40 +60
+80 +100 +120 +140
TEMPERATURE (oC)
TEMPERATURE (oC)
FIGURE 5. SNR vs TEMPERATURE
FIGURE 6. TOTAL HARMONIC DISTORTION vs TEMPERATURE
4.0 3.5 3.0 2.5 LSB 2.0 1.5 1.0 0.5
1.0 VDD = 5V, VREF+ = 4V fIN = 100kHz 0.75 FS = 20MHz
VDD = 5V, VREF + = 4V fIN = 100kHz
FS = 20MHz LSB 0.5 FS = 15MHz FS = 15MHz 0.25
0 -60
-40
-20
0
+20
+40
+60
+80 +100 +120 +140
0 -60
-40
-20
0
+20
+40
+60
o
+80 +100 +120 +140
TEMPERATURE (oC)
TEMPERATURE ( C)
FIGURE 7. INL vs TEMPERATURE
FIGURE 8. DNL vs TEMPERATURE
4-1496
HI-5700 Typical Performance Curves
8 VDD = 5V, VREF+ = 4V 7 FS = 20MHz 6 LSB 5 4 0.5 3 2 0 -60 FS = 15MHz FS = 15MHz LSB 1.0 FS = 20MHz 1.5
(Continued)
2.0 VDD = 5V, VREF + = 4V
-60
-40
-20
0
+20
+40
+60
+80 +100 +120 +140
-40
-20
0
+20
+40
+60
+80 +100 +120 +140
TEMPERATURE (o C)
TEMPERATURE (o C)
FIGURE 9. OFFSET VOLTAGE vs TEMPERATURE
FIGURE 10. FULL SCALE ERROR vs TEMPERATURE
35
VDD = 5V, VREF + = 4V
1.0 VDD = 5V, VREF + = 4V 0.5 tOD PSRR VOS tHOLD LSB 0 PSRR FSE
30 CLOAD = 30pF 25 ns 20
15
-0.5
10 -60
-40
-20
0
+20
+40
+60
+80 +100 +120 +140
-1.0 -60
-40
-20
0
+20
+40
+60
+80 +100 +120 +140
TEMPERATURE (oC)
TEMPERATURE (oC)
FIGURE 11. OUTPUT DELAY vs TEMPERATURE
200 190 180 170 160 150 mA 140 130 120 110 100 90 80 -60 -40 -20 0 +20 +40 +60
o
FIGURE 12. POWER SUPPLY REJECTION vs TEMPERATURE
180 170 VDD = 5V, VREF + = 4V 160 TA = 25o C 150 140 130 tAB 120 D= 110 tAB + tS 100 90 80 70 60 50 40 30 0.1 1
VDD = 5V, VREF + = 4V
D = 50%
mA
FS = 20MHz
D = 25%
FS = 1MHz
D = 10%
+80 +100 +120 +140
10
100
TEMPERATURE ( C)
CLOCK FREQUENCY (MHz)
FIGURE 13. SUPPLY CURRENT vs TEMPERATURE
FIGURE 14. SUPPLY CURRENT vs CLOCK DUTY CYCLE
4-1497
HI-5700
TABLE 1. PIN DESCRIPTION PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME CLK D7 D6 D5 D4
1/ 4R
DESCRIPTION Clock Input Bit 7, Output (MSB) Bit 6, Output Bit 5, Output Bit 4, Output
1/ 4th
output word, plus an additional comparator to detect an overflow condition. The CMOS HI-5700 works by alternately switching between a "Sample" mode and an "Auto Balance" mode. Splitting up the comparison process in this CMOS technique offers a number of significant advantages. The offset voltage of each CMOS comparator is dynamically canceled with each conversion cycle such that offset voltage drift is virtually eliminated during operation. The block diagram and timing diagram illustrate how the HI-5700 CMOS flash converter operates. The input clock which controls the operation of the HI-5700 is first split into a non-inverting 1 clock and an inverting 2 clock. These two clocks, in turn, synchronize all internal timing of analog switches and control logic within the converter. In the "Auto Balance" mode (1), all 1 switches close and 2 switches open. The output of each comparator is momentarily tied to its own input, self-biasing the comparator midway between GND and VDD and presenting a low impedance to a small input capacitor. Each capacitor, in turn, is connected to a reference voltage tap from the resistor ladder. The Auto Balance mode quickly precharges all 256 input capacitors between the self-bias voltage and each respective tap voltage. In the "Sample" mode (2), all 1 switches open and 2 switches close. This places each comparator in a sensitive high gain amplifier configuration. In this open loop state, the input impedance is very high and any small voltage shift at the input will drive the output either high or low. The 2 state also switches each input capacitor from its reference tap to the input signal. This instantly transfers any voltage difference between the reference tap and input voltage to the comparator input. All 256 comparators are thus driven simultaneously to a defined logic state. For example, if the input voltage is at mid-scale, capacitors precharged near zero during 1 will push comparator inputs higher than the self bias voltage at 2; capacitors precharged near the reference voltage push the respective comparator inputs lower than the bias point. In general, all capacitors precharged by taps above the input voltage force a "low" voltage at comparator inputs; those precharged below the input voltage force "high" inputs at the comparators. During the next 1 Auto-Balancing state, comparator output data is latched into the encoder logic block and the first stage of encoding takes place. The following 2 state completes the encoding process. The 8 data bits (plus overflow bit) are latched into the output flip-flops at the next falling clock edge. The Overflow bit is set if the input voltage exceeds VREF + - 0.5 LSB. The output bus may be either enabled or disabled according to the state of CE1 and CE2 (See Table 2). When disabled, output bits assume a high impedance state. As shown in the timing diagram, the digital output word becomes valid after the second 1 state. There is thus a one and a half cycle pipeline delay between input sample and digital output. "Data Output Delay" time indicates the slight time delay for data to become valid at the end of the 1
Point of Reference Ladder
V DD GND
3
Digital Power Supply Digital Ground
3
/4R
/4th Point of Reference Ladder
D3 D2 D1 D0 OVF CE2 CE1 V REF + AV DD AGND AGND AV DD
1/ 2R
Bit 3, Output Bit 2, Output Bit 1, Output Bit 0, Output (LSB) Overflow, Output Three-State Output Enable Input, Active High. (See Table 2) Three-State Output Enable Input, Active Low. (See Table 2) Reference Voltage Positive Input Analog Power Supply, +5V Analog Ground Analog Ground Analog Power Supply, +5V
1/ 2
Point of Reference Ladder
AV DD AGND AGND AV DD V REF V IN
Analog Power Supply, +5V Analog Ground Analog Ground Analog Power Supply, +5V Reference Voltage Negative Input Analog Input
TABLE 2. CHIP ENABLE TRUTH TABLE CE1 0 1 X X's = Don't Care. CE2 1 1 0 D0 - D7 Valid Three-State Three-State Valid Valid Three-State OVF
Theory of Operation
The HI-5700 is an 8-bit analog-to-digital converter based on a parallel CMOS "flash" architecture. This flash technique is an extremely fast method of A/D conversion because all bit decisions are made simultaneously. In all, 256 comparators are used in the HI-5700: (28-1) comparators to encode the
4-1498
HI-5700
HA-5033 +9V TO +12V 100 CLOCK INPUT 1 CLK 50 OUTPUT PINS DIGITAL VDD TO ANALOG +5V 10F TO ANALOG GND DIGITAL GROUND OUTPUT PINS 0.01F 2 D7 3 D6 4 D5 5 D4 6 1/4R 7 VDD 8 GND 9 3/4R 10 D3 11 D2 12 D1 13 D0 14 OVF VIN 28 VREF - 27 AVDD 26 AGND 25 AGND 24 AVDD 23
1
0.01F
10F
ANALOG SIGNAL INPUT
+9V TO +12V
0.01F
10F
0.01F
10F
ANALOG VDD (+5V)
/2R 22
AVDD 21 AGND 20 AGND 19 AVDD 18 VREF + 17 CE1 16 CE2 15 +5V
ANALOG GROUND
0.01F
10F PRECISION DC REFERENCE
0.01F
10F
FIGURE 15. TEST CIRCUIT
Applications Information
Voltage Reference The reference voltage is applied across the resistor ladder between VREF + and V REF -. In most applications, V REF - is simply tied to analog ground such that the reference source drives VREF +. The reference must be capable of supplying enough current to drive the minimum ladder resistance of 235 over temperature. The HI-5700 is specified for a reference voltage of 4.0V, but will operate with voltages as high as the VDD supply. In the case of 4.0V reference operation, the converter encodes the analog input into a binary output in LSB increments of (VREF + - VREF -)/256, or 15.6mV. Reducing the reference voltage reduces the LSB size proportionately and thus increases linearity errors. The minimum practical reference voltage is about 2.5V. Because the reference voltage terminals are subjected to internal transient currents during conversion, it is important to drive the reference pins from a low impedance source and to decouple thoroughly. Again, ceramic and tantalum (0.01F and 10F) capacitors near the package pin are recommended. It is not necessary to decouple the 1/4R, 1/2R, and 3/4R tap point pins for most applications. It is possible to elevate VREF - from ground if necessary. In this case, the VREF - pin must be driven from a low impedance reference capable of sinking the current through the resistor ladder. Careful decoupling is again recommended. Digital Control and Interface The HI-5700 provides a standard high speed interface to external CMOS and TTL logic families. Two chip enable inputs control the three-state outputs of output bits D0 through D7 and the Overflow (OVF) bit. As indicated in the Truth Table, all output bits are high impedance when CE2 is low, and output bits D0 through D7 are independently controlled by CE1. Although the Digital Outputs are capable of handling typical data bus loading, the bus capacitance charge/discharge currents will produce supply and local group disturbances. Therefore, an external bus driver is recommended. Clock The clock should be properly terminated to digital ground near the clock input pin. Clock frequency defines the conversion frequency and controls the converter as described in the "Theory of Operation" section. The Auto Balance 1 half cycle of the clock may be reduced to approximately 20ns; the Sample 2 half cycle may be varied from a minimum of 25ns to a maximum of 5s. Signal Source A current pulse is present at the analog input (VIN) at the beginning of every sample and auto balance period. The transient current is due to comparator charging and switch feedthrough in the capacitor array. It varies with the amplitude of the analog input and the converter's sampling
4-1499
HI-5700
rate. The signal source must absorb these transients prior to the end of the sample period to ensure a valid signal for conversion. Suitable broad band amplifiers or buffers which exhibit low output impedance and high output drive include the HA-5004, HA-5002, and HA-5003. The signal source may drive above or below the power supply rails, but should not exceed 0.5V beyond the rails or damage may occur. Input voltages of -0.5V to +0.5 LSB are converted to all zeroes; input voltages of VREF+ -0.5 LSB to VDD +0.5V are converted to all ones with the Overflow bit set. Full Scale Offset Error Adjustment In applications where accuracy is of utmost importance, three adjustments can be made; i.e., offset, gain, and reference tap point trims. In general, offset and gain correction can be done in the preamp circuitry. Offset Adjustment Offset correction can be done in the preamp driving the converter by introducing a DC component to the input signal. An alternate method is to adjust VREF- to produce the desired offset. It is adjusted such that the 0 to 1 code transition occurs at 0.5 LSB. Gain Adjustment In general, full scale error correction can be done in the preamp circuitry by adjusting the gain of the op amp. An alternate method is to adjust the VREF+ voltage. The reference voltage is the ideal location. Quarter Point Adjustment The reference tap points are brought out for linearity adjustment or creating a nonlinear transfer function if desired. It is not necessary to decouple the 1/4R, 1/2R, and 3/ 4R tap points in most applications. Power Supplies The HI-5700 operates nominally from 5V supplies but will work from 3V to 6V. Power to the device is split such that analog and digital circuits within the HI-5700 are powered separately. The analog supply should be well regulated and "clean" from significant noise, especially high frequency noise. The digital supply should match the analog supply within about 0.5V and should be referenced externally to the analog supply at a single point. Analog and digital grounds should not be separated by more that 0.5V. It is recommended that power supply decoupling capacitors be placed as close to the supply pins as possible. A combination of 0.01F ceramic and 10F tantalum capacitors is recommended for this purpose as shown in the test circuit. Reducing Power Consumption Power dissipation in the HI-5700 is related to clock frequency and clock duty cycle. For a fixed 50% clock duty cycle, power may be reduced by lowering the clock frequency. For a given conversion frequency, power may be reduced by decreasing the Auto-Balance (1) portion of the clock duty cycle. This relationship is illustrated in the
BINARY OUTPUT CODE DECIMAL COUNT 511 255 254 MSB OVF 1 0 0 D7 1 1 1 D6 1 1 1 D5 1 1 1 D4 1 1 1 D3 1 1 1 D2 1 1 1 D1 1 1 1 LSB D0 1 1 0
TABLE 3. CODE TABLE INPUT VOLTAGE VREF + = 4.0V VREF - = 0.0V (V) 4.000 3.9766 3.961
CODE DESCRIPTION Overflow (OVF) Full Scale (FS) FS - 1 LSB
3/4 FS
2.992
192
0
1
1
0
0
0
0
0
0
1/2 FS
1.992
128
0
1
0
0
0
0
0
0
0
1/4 FS
0.992
64
0
0
1
0
0
0
0
0
0
1 LSB Zero
0.0078 0
1 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
1 0
The voltages listed above represent the ideal transition of each output code shown as a function of the reference voltage.
4-1500
HI-5700 Glossary of Terms
Aperture Delay: Aperture delay is the time delay between the external sample command (the rising edge of the clock) and the time at which the signal is actually sampled. This delay is due to internal clock path propagation delays. Aperture Jitter: This is the RMS variation in the aperture delay due to variation of internal 1 and 2 clock path delays and variation between the individual comparator switching times. Differential Linearity Error (DNL): The differential linearity error is the difference in LSBs between the spacing of the measured midpoint of adjacent codes and the spacing of ideal midpoints of adjacent codes. The ideal spacing of each midpoint is 1.0 LSB. The range of values possible is from -1.0 LSB (which implies a missing code) to greater than +1.0 LSB. Full Power Input Bandwidth: Full power input bandwidth is the frequency at which the amplitude of the fundamental of the digital output word has decreased 3dB below the amplitude of an input sine wave. The input sine wave has a peak-to-peak amplitude equal to the reference voltage. The bandwidth given is measured at the specified sampling frequency. Full Scale Error (FSE): Full Scale Error is the difference between the actual input voltage of the 254 to 255 code transition and the ideal value of VREF + - 1.5 LSB. This error is expressed in LSBs. Integral Linearity Error (INL): The integral linearity error is the difference in LSBs between the measured code centers and the ideal code centers. The ideal code centers are calculated using a best fit line through the converter's transfer function. LSB: Least Significant Bit = (VREF + - VREF -)/256. All HI5700 specifications are given for a 15.6mV LSB size VREF + = 4.0V, VREF - = 0.0V. Offset Error (VOS): Offset error is the difference between the actual input voltage of the 0 to 1 code transition and the ideal value of VREF - + 0.5 LSB, VOS Error is expressed in LSBs. Power Supply Rejection Ratio (PSRR): PSRR is expressed in LSBs and is the maximum shift in code transition points due to a power supply voltage shift. This is measured at the 0 to 1 code transition point and the 254 to 255 code transition point with a power supply voltage shift from the nominal value of 5.0V. Signal to Noise Ratio (SNR): SNR is the ratio in dB of the RMS signal to RMS noise at specified input and sampling frequencies. Signal to Noise and Distortion Ratio (SINAD): SINAD is the ratio in dB of the RMS signal to the RMS sum of the noise and harmonic distortion at specified input and sampling frequencies. Total Harmonic Distortion (THD): THD is the ratio in dBc of the RMS sum of the first five harmonic components to the RMS signal for a specified input and sampling frequency.
4-1501
HI-5700 Die Characteristics
DIE DIMENSIONS: 154.3 x 173.2 x 19 1mils METALLIZATION: Type: Si - Al Thickness: 11kA 1kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA TRANSISTOR COUNT: 8000 SUBSTRATE POTENTIAL (Powered Up): V+
Metallization Mask Layout
HI-5700
VREFAVDD CLK VIN D5 D6 D7
4
D4
3
2
1
28
27
26
5 25
AGND
1/4R VDD
6 7 24
AGND
23
VDD
AVDD
7 22
1/ R 2
GND
8 21
AVDD
GND
8 20
AGND
3/4R
9
D3
10
19
AGND
11
D2
12
D1
13
D0
14
OVF
15
CE2
16
CE1
17
VREF +
18
AVDD
4-1502

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Price & Availability of HI3-5700A-9

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